Ventana has launched its Veyron V2 RISC-V processor design aimed toward information heart operators and hyperscalers in an effort to assist them design their servers with rather more precision and at a lot quicker scale.
Shortly after launching its Veyron V1 chiplets earlier this 12 months, the corporate has come out with a successor that may provide an IO hub and accelerators which have partnered with the UCI Categorical chiplet connectivity normal to supply 192 cores per socket.
In a conceptual instance, six 32-core V2 chiplets had been linked to the IO hub via UCI-Categorical and had been prolonged with domain-specific acceleration. The IO hub is also linked to reminiscence and parts via DDR5 and PCIe 5.0 controllers. Nonetheless, the agency says organizations can swap out DDR5 controllers for HBM3 controllers in the event that they select, in response to Subsequent Platform.
Hyperscalers are taking note of Ventana
The explanation Ventana has launched its subsequent technology after launching the Veyron V1 earlier this 12 months is the truth that this model used the Bunch of Wires (BoW) normal for interconnecting chiplets – which was the most effective out there on the time.
However Intel then launched the UCI-Categorical normal final March, which proved to be the superior choice for connecting chiplets, and Ventana wasted no time integrating this know-how into the subsequent model of its chip know-how.
Some of the promising points of this element is benchmarking, the place the corporate’s numbers present that the 192-core Veyron 2 RISC-V CPU beats a number of opponents fairly simply on throughput.
These embody 64-core Arm Neoverse V2, 56-core Intel Xeon SPR 8400+, 96-core AMD EPYC Genoa 9654 and 12-core AMD EPYC Bergamo 9754 CPUs.
The Ventana Veyron V2 processor boasted 23% extra integers throughout the board than AMD’s Bergamo CPU, which is likely one of the quickest processors on the market, making this a extremely aggressive choice for companies.
The bottom mannequin of the Veyron V2 design comes with 4 chiplets for 128 cores and eight DDR5 RAM channels, and can enter manufacturing within the third quarter of subsequent 12 months. It is because the manufacturing depends on the UCI-Categorical 1.1 PHY normal to be out there.
